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Academics > Departments

Electronics and Communication Engineering (ECE)

Dr. M. V. Ganeswara Rao

Associate Professor |

B.Tech:- Electronics and Communication Engineering, JNTUH Hyderabad, 2002
M.Tech:- Digital Electronics and Communication Systems, JNTUH Hyderabad, 2008
Ph.D: VLSI, Image Processing, JNTUK, Kakinada, 2021

Teaching Experience: 19 years
Industrial experience: —

AICTE ID: 1-457749079
SVECW ECAP ID: 412
Vidwan ID: 196149
Ratification Status: Ratified

  • PG projects guided: 15
  • UG projects guided: 30
  • Journals published: 25
  • Conferences attended: 06.
  • Guest lecturers delivered:01
  • Member of IETE :-ID: M-223318
  • Member of ISTE :- ID: LM 65889
  • Member of IE :- ID:M-158149-4
  • VLSI Architecture for Image Processing
  • VLSI circuit Design
  • Image processing
  • Deep learning
  • Processor design

25

6

  • Granted for a fund of INR 10 Lakhs from AICTE (MODROBS ) , Government of India for one years starting from june 2010.
  • Granted for a fund of INR 64.55 Lakhs from Ministry of Electronics and Information technology, under Chip to Startup (C2S), Government of India for five years starting from January 2024.
  • VLSI Circuits design
  • Memory optimization for Deep learning
  • Advances in science, technology and Engineering systems journal
  • International Conference on Computational Intelligence, Networks and Security, ICCINS-2023
  • Completed 8 week NPTEL Course on “Accreditation and Outcome based Education”, from, IIT Kharagpur.
  • Completed 8 week NPTEL Course on “Embedded Systems Design with ARM”, from, IIT Kharagpur.
  • Completed 12 week NPTEL Course on “Operating Systems Fundamentals”, IIT Kharagpur.
  • A one week workshop on “Microcontrollers & It’s Applications, 17th-21st November,2014\
  • A one week Workshop on “Embedded Systems Programming for innovation” 27 November to 3 December, 2023
  • Participated in 3 Days workshop on “DSP processors” conducted by Gudlavalleru engineering College Gudlavalleru. 3th & 5th February 2006.
  • Participated in A 2 Day workshop on “VLSI Design” conducted by Gudlavalleru engineering College, Gudlavalleru during 9th & 10th February 2007.
  • Participated in A 3 Day workshop on “Embedded System Design using AT89C51 ” conducted byWienyordTechnologiesHyderabadfromJune14,2007toJune 16,2007
  • Participated in A 3 Day workshop on “ASIC Design using System veri Log“ conducted by Visvaswaraya Engineering College, Bangalore from October25,2007toOctober27,2007.
  • Participated in faculty development programme “Industrial Design& Delivery” conducted by NITTR from September3,2007toSeptember8,2007.
  • Participatedinfacultydevelopmentprogramme“Studentcounseling&CarrierGuidance”conductedbyNITTRfrom July20,2008toJuly21,2008.
  • Participated in A 5 day workshop “MISSION10X conducted by WIPRO from 17th February to 21stFebruary2009.
  • ParticipatedintheTwoDayWorkshopon“DigitalDesignSimplified-TakingDesignfromSimulation to Layout Extraction ” conducted by Coreel Technologies from 30thApril to 1st May-2010.
  • Participated in the national convection for Academic and research organized by free software movement of India from 16thto18th December,2010.
  • ParticipatedinIUCEEworkshopconductedatMITSMadanapallion“ImageProcessing”during5th-9thJuly,2010.
  • ParticipatedinManagementDevelopmentProgramforSeniorRepresentativesofTEQIPInstitutions in AP from September 2, 2013 to September 2, 2013 conducted by Indian School of business (ISB),Hyderabad
  • Participated in the workshop on “Embedded Systems and VLSI Design in Robotics” conducted by I2IT Pune from April1,2013to April5,2013.
  • One Week FDP on Recent Trends in “Computer Architecture, VLSI & Embedded System”, 08-06-2020 to 13-06-2020
  • One Week FDP on “NAAC awareness program for faculty”, 05-05-2020 to 14-05-2020
  • 4 Week FDP on Python3.4.3 during January Semester by Gurunanak Institute of Technology, Hyderabad. 19-05-2020 to 26-05-2020
  • An online credit course on “Intellectual Property Rights & Innovation” 29-04-2019 to 29-04-2019
  • AICTE Short term training Program on “National Educational Policy (NEP) 2020, 01-05-2021 to 01-05-2021
  • National Lavel workshop on “Digital Design of FPGA through Verilog”, ” 19-06-2021 to 26-o6-2021
  • 5 day online FDP on “Inculcating universal Human values in technical education” organized by AICTE from 19th December to 23rd December, 2022
  • A Five day face to Face UHV-II FDP organized by the AICTE at JNTUA from 12th December to 16th December 2023.
  • AICTE approved FDP on “design Challenges opportunities in VLSI” organized by SRKR Engineering college , Bhimabvaran, held during 9th October to 13th October, 2023
  • NAAC college level champion
  • Department ECAP Coordinator
  • Department CollPoll Coordinator
  • VLSI Special lab In-charge
  • MPMC Lab In-charge